A semiconductor device package type and method that is recently come into use is the multi-chip package (MCP). A multi-chip package can include multiple integrated circuit (IC) chips contained in a single package. This can raise chip packaging density, which can meet the demand for reductions in component/device size.
Multi-chip packages can be classified into planar packaging types, in which multiple chips are mounted on the same substrate that forms a plane, and vertical packaging types, in which multiple chips are arranged in vertical direction to form a stacked structure.
A conventional planar packaging type semiconductor device is set forth in a side cross sectional view in FIG. 31. The conventional semiconductor device is designated by the general reference character 101, and can include semiconductor chips 103 and 104, each having memory circuit formed thereon, and arranged in the same plane.
A known conventional vertical packaging type semiconductor device is shown in FIG. 32 in a side cross sectional view. In this example, conventional semiconductor device 108 can include semiconductor chips 106 and 107 stacked on a substrate 105. Circuit faces for semiconductor chips (106 and 107) can be turned upward (i.e., toward the top of the figure in FIG. 32).
Another conventional vertical packaging type semiconductor device is shown in a side cross sectional view in FIG. 33, and designated by the general reference character 112. FIG. 33 shows a chip-on-chip (COC) device 112 in which semiconductor chips 110 and 111 are arranged on a substrate 109 with their circuit faces opposing one another.
A conventional method of manufacturing a vertical packaging type multi-chip semiconductor device will now be described.
Referring to FIG. 34(a), in a conventional method of manufacturing a COC type device, a first step is to mount a lower side of semiconductor chip 110 onto a substrate 109 by dripping or applying an adhesive 113 onto the substrate 109 and then attaching semiconductor chip 110 to the substrate 109.
Referring to FIG. 34(b), the adhesive 113 may then be cured and bumps 110a can be formed on the circuit face of semiconductor chip 110.
Referring to FIG. 34(c), an upper side (e.g., a circuit face) of semiconductor chip 111 can be mounted onto semiconductor chip 110 so that electrodes of the semiconductor chips (110 and 111) are brought into contact with one another. The semiconductor chips (110 and 111) are then joined by a hot press fit. Thereafter, the semiconductor chips (110 and 111) are sealed with a resin to obtain the semiconductor device 112 shown in FIG. 33.
As shown in FIG. 34(c), in the manufacture of a conventional semiconductor device employing a vertical type multi-chip package, an adhesive may be uneven in thickness after curing. This can cause a tilt to occur in the semiconductor device (e.g., 110) with respect to a substrate surface (e.g., 109). Such a tilt can result in uneven force being applied to different portions of semiconductor device 110 when the other semiconductor device 111 is attached thereto. Such uneven force can damage circuit components on the face of semiconductor device 110.
Semiconductor devices employing vertical packaging type arrangements for a multi-chip package can reduce overall device sizes. However, such arrangements can have drawbacks in the event one or more of the included semiconductor chips consumes a large amount of power. In particular, when a semiconductor device consumes a large amount of a power, it generates a correspondingly large amount of heat. Conventional vertical packaging types, like those described above, may not provide sufficient heat dissipation. As a result, chips within the multi-chip package can overheat, resulting in malfunctions or damage to the device.
To address heat dissipation needs for a multi-chip package, conventional techniques are proposed that include placing a heat dissipating metal plate above an upper side of semiconductor chip or between semiconductor chips. One such conventional example is disclosed in Japanese Patent Publication 2000-294723A.
The technique disclosed in the above publication can have drawbacks in certain applications. For example, a semiconductor chip with an analog circuit can be mounted with a semiconductor chip with a digital circuit in order to provide multiple device functions. However, in such an arrangement noise generated from one semiconductor chip can adversely affect the other semiconductor chip.
That is, while the above conventional technique aims to improve heat dissipation capabilities, such a technique does not provide a countermeasure against noise. Therefore, multi-chip packages which include a heat dissipating metal plate that seek to include an analog circuit, which can be particularly susceptible to noise, may more readily draw in noise, causing a malfunction and/or a decline in reliability.
This can make it difficult to reduce overall package size when employing a vertical packaging type multi-chip package.
In light of the above, it would be desirable to arrive at a vertical packaging type semiconductor device and manufacturing method that can ensure high reliability by providing sufficient heat dissipation, while at the same time reducing or eliminating susceptibility to noise, as compared to conventional approaches.